Brief Course Outline
- Introduction to VHDL, Verilog tools and design methodology
- Design Units in VHDL/Verilog
- Timing and Simulation
- Basic elements in VHDL/Verilog
- Behavioral Modeling and Structural Modeling
- Advanced Concepts in VHDL/Verilog
- Altera FPGA Architecture
- System on a Chip (SoC)
- Introduction to Nios II soft core processor
- Applications of FPGAs and Nios II Systems (Robotics, LCD Display)
Course duration – 8 weeks, 4 hour session per week
Course is conducted by qualified University Lecturer.
Group class (3 – 6 students) – Rs. 15,000 per one student
Fees can be paid in two installments.
Lecture notes and take home assignments / tutorials will be given for every session.
Individual attention is guaranteed.
Wi-Fi and Library facilities are available.
Air Conditioned Lecture Rooms.
For more details please contact us.