FPGA System Design & Optimization using VHDL/ Verilog

Altera-de0-Scion-Sri-Lanka

Brief Course Outline

  1. Introduction to VHDL, Verilog tools and design methodology
  2. Design Units in VHDL/Verilog
  3. Timing and Simulation
  4. Basic elements in VHDL/Verilog
  5. Behavioral Modeling and Structural Modeling
  6. Advanced Concepts in VHDL/Verilog
  7. Altera FPGA Architecture
  8. System on a Chip (SoC)
  9. Introduction to Nios II soft core processor
  10. Applications of FPGAs and Nios II Systems (Robotics, LCD Display)

Course duration – 8 weeks, 4 hour session per week

Course is conducted by qualified University Lecturer.

Fee structure 
Group class (3 – 6 students) – Rs. 14,000 per one student

Fees can be paid in two installments.

Lecture notes and take home assignments / tutorials will be given for every session.

Individual attention is guaranteed.

Wi-Fi and Library facilities are available.

Air Conditioned Lecture Rooms.

For more details please contact us.